Last week we announced that Intel will collaborate with Microsoft in the creation of homomorphic encryption for DARPA, and today Intel announced all the details regarding this collaboration with the United States Defense Advanced Research Projects Agency, which It will last for at least 3 years, where the company will provide DARPA with its most advanced ASIC architectures in a 10nm manufacturing process with production on US soil.
Intel and the US Defense Advanced Research Projects Agency (DARPA) today announced a three-year partnership to advance the development of domestically manufactured application-specific structured integrated circuit (ASIC) platforms. The Structured Array Hardware for Automatically Realized Applications (SAHARA) association enables the design of custom chips that include state-of-the-art security countermeasures technologies. A reliable and secure domestic source of leading-edge semiconductors remains critical to America.
"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chips and enhanced security protection, and all of this is manufactured in the United States from start to finish. This will allow developers of commercial electronic systems and defense to rapidly develop and implement custom chips based on Intel's advanced 10nm semiconductor process, "said José Roberto Álvarez, Senior Director, Office of the CTO, Intel Programmable Solutions Group.
Why It Matters: As the only US-based manufacturer of advanced semiconductors, Intel promotes supply chain security by using facilities within the United States to manufacture, assemble, and test custom chips for the SAHARA association.
"Structured ASICs have advantages over FPGAs that are widely used in many Department of Defense applications. By partnering with Intel in the SAHARA program, DARPA aims to transform current and future capabilities into structured ASIC implementations with significantly higher performance and higher performance. lower power consumption, "said Serge Leef, program director in DARPA's Office of Microsystems Technology.
"SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support the manufacturing of the resulting silicon in zero-trust environments." In addition, Intel will establish national manufacturing capabilities for structured ASICs in its 10nm process. "
How it works: In collaboration with the University of Florida, Texas A&M, and the University of Maryland, Intel will develop security countermeasure technologies that improve data and intellectual property protection against reverse engineering and counterfeiting. College teams will use rigorous verification, validation, and new attack strategies to test the security of these chips. Security countermeasures technologies will be integrated into Intel's structured ASIC design flow.
Intel will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering costs compared to traditional ASICs. Intel will manufacture these chips using its 10nm manufacturing process with advanced die-to-die interface bus interconnect and multi-die interconnects bridge packaging technology to integrate multiple heterogeneous dies into a single package.
About Intel eASICs: Intel eASIC devices are structured ASICs, a technology intermediate between field-programmable gate arrays (FPGAs) and standard cell ASICs. These devices offer a lower unit cost and run on less power compared to FPGAs, and offer faster time to market and lower non-recurring engineering costs compared to standard cell ASICs.
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