Thanks to the AMD EPYC GENOA processors, intended for servers, more information has been leaked about the next AMD microarchitecture, Zen4, and it is that at least these processors will support the AVX3-512 instruction set in addition to BFloat16 and " other ISA instructions ".
With the support of the AVX-512 instruction, the only strong point of Intel Xeon processors is thus eliminated at a stroke, which is always analyzed in benchmarks that take advantage of said instruction to inflate the performance advantages over their rival. If this leak is correct, no more slides with handpicked benchmarks to show an unrealistic advantage.
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| Concept of an AMD EPYC GENOA CPU |
It should be remembered that yesterday it was indicated again that these processors will arrive with a configuration of up to 96 cores and 192 processing threads accompanied by a dodeca (12) -channel memory configuration, which in this case the information is expanded indicating that it will natively support DDR5 RAM @ 5200 MHz making use of the SP5 socket (LGA-6096), access to a maximum of 128 PCI-Express 5.0 lanes (160 for Dual CPU configurations), and the top-of-the-range model of 96 cores would have a TDP of 320W (cTDP of 400W).
On the other hand, it is indicated that the size of the socket is 72 x 75.4 mm, and this large increase is linked to the increase in the number of cores in the form of a chiplet design with 12 dies (CCD) with 8 cores each.
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